This invention relates to integrated circuit devices, and more particularly to circuitry on an integrated circuit that can be used to receive a serial data signal at very high bit rates (e.g., in the range of about 10 gigabits per second (10 Gbps or 10 G) and higher).
Industry standards have been developed that call for transmission of serial data signals between relatively closely spaced integrated circuits (“chips”) in a system. One typical application is the so-called 10 Gigabit Small Form Factor Pluggable module. The whole module specification for this standard is known as XFP, and the interface specification for this standard is known as XFI. This module supports telecommunication applications such as SONET OC-192 and G.709 “OUT-2”, and data communication applications such as 10 Gb/s Ethernet and 10 Gb/s Fibre Channel. The serial link in this standard includes a connector and a pair of printed circuit board (“PCB”) traces of less than 200 mm. The channel attenutation is about 6 db at 5.5 GHz. Providing enough equalization and, at the same time, supporting such high data rates (i.e., in the range of about 10 Gbps and higher) in the circuitry that receives such a signal is a very challenging technical task.
Another challenging task is to provide good and efficient conversion of data from the serial form in which it is received from a channel of the type described above to a parallel form in which it can be more easily handled by circuitry downstream from the receiver. A related problem is the reverse process on the transmitter side (i.e., converting parallel data to serial form for extremely high-speed serial output).